SESSION 5: An Introduction to SEQUENTIAL LOGIC
This final session is an introduction to another branch of logic circuits, which as the name suggests,
involves time. The output of a sequential circuit depends not just on the value of inputs at the present
time, but on value of inputs that have been present in the past. This is very different from the circuits
in the previous sessions which are called combinational logic. Here the output value is dependent only on
the value of inputs present at that instant in time. Sequential circuits are made up of the same basic
gates of AND, OR and NOT, as the combinational circuits but configured in such a way as to form storage.
The circuits have "memory" which allows previous input values to be stored an used later. The simplest of
these is called a Latch. The basic latch circuit can be based on NAND gates or NOR gates. Remember
a NAND gate is formed by an AND followed by a NOT, and a NOR formed by an OR gate followed by a NOT.
A latch formed from NAND gates
The action of this circuit is as follows. The inputs marked R and S are both logic "1" at the start. Assume
the output of AND gate_A is a "1". This means that Q, which is the second input, must be "1". The output of
AND gate_B must "0" for Q, which is NOT AND gate_B, to be "1". The S input is "1" so the other
input, NOT Q, must be "0". We started with AND gate_A as "1" therefore NOT AND gate_A must be "0".
As NOT AND gate_A is NOT Q then all the logic levels are consistent and this is a stable circuit, i.e. one where the output
levels will not change over time without a change of inputs.
First Test
If input S goes to "0" and back to "1" then nothing will change as the other input to AND gate_B is already
"0".
Second Test
If input R goes to "0" then AND gate_A will change to "0". Then NOT AND gate_A, which is also NOT Q
will go to "1". Then as both inputs to AND gate_B are "1" the output from AND gate_B will go to "1".
Then NOT AND gate_B which is also "Q" goes to "0".
third Test
If input R goes to "0" and back to "1" then nothing will change as the other input to AND gate_A is already
"0".
four Test
If input S goes to "0" then AND gate_B will change to "0". Then NOT AND gate_B, which is also Q
will go to "1". Then as both inputs to AND gate_A are "1" the output from AND gate_A will go to "1".
Then NOT AND gate_B which is also "Q" goes to "0".
five Test
If input S goes to "0" and back to "1" then nothing will change as the other input to AND gate_B is already
"0".
PRACTICAL WORK
First build the NAND latch above using one quad 2-input AND chip and one hex inverter chip. The outputs, Q and NOT Q,
should be connected two of the lamp monitors.
Second connect a logic switch to the "R" input and another to "S" input.
Third check the operation of the circuit and see if it follows the description above.
Finally look at the latch bellow, made from NOR gates. See if you can work out how it works, then build and check in the same way as
you checked the NAND latch. make a note of your results in your log book.
A latch formed from NOR gates