TRIAL ONE BUILDING PAGE


TRIAL ONE BUILDING: An introduction to the techniques used in building digital circuits.


SECTION INDEX
  1. Revision of Combinational Logic and Introduction to the Digital Logic Trainer.
  2. Introduction to the Practical Task and the creation of segment select circuits.
  3. Details of the 7 Segment Display and the use of segment selection circuits to drive it.
  4. The use of a CMOS 4511 BCD to 7 Segment Latch Decoder Driver as part of Prcatical Task.


1. Building with Combinational Logic circuits and the Digital Logic Trainer.
An important feature of building is to build sections and test them during construction, rather than leaving the testing to the end. This helps to isolate where the problem is making correction easier. Often complex systems are designed in this way providing ready made sections to test. This technique will be seen later in section three. This first section is an introduction to the use of the digital trainer and the CMOS logic devices used in the trial.
The practical task is to use the digital trainer to test the operation of a CMOS 4081 Quad 2 input AND gate. Although simple, this task introduces many of the practical details needed for the work of later sections. The diagram below shows the layout of the 4081 AND gate.



CMOS 4081 Quad 2 in AND gate pinout

Choose an AND gate to use, top left hand corner of chip, for example. Pin 1 and 2 are inputs. Connect Pin 1 to switch 1 and Pin 2 to switch 2. VSS, pin 7, should be connected to 0V on the digital trainer. VDD, pin 14, should be connected to +V digital trainer. The circuit is now ready for testing.

RETURN TO SECTION 1
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2. Introduction to the Practical Task and the creation of segment select circuits.



The task was to decode the switch values and display the decimal equivalent value on a seven segment display. The first stage of this task was to calculate the boolean expression for each of the seven segments in terms of the two logic switch values. The circuit using AND, OR and NOT for each of the segments was then designed. [Boolean Algebra was used to simplify the expression before designing the circuit]. The diagrams below shows the arrangement of the seven segments on the seven segment display.




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3. Details of the 7 Segment Display and the use of segment selection circuits to drive it. .

A driver circuit is required to drive each segment as logic output from a gate is not able to supply enough current to drive the LED. The seven circuits required are usually supplied as one package for ease of use. The image below shows the package designed for this trial. It has a connector with 16 pins so that it can be used with the digital trainer.





The connection of the driver board to the 7 segment display is a good example of a circuit section suitable for building and testing separately. The image below shows the way in which the two devices are connected on the prototype board.



Driver circuit connections
(Pin 1, segment a, is to the left of the "notch"
viewed from the top of the 16 pin connector)

Use of the Driver Circuit
The seven inputs, "a" to "g", are connected to the corresponding outputs on the logic circuits from the digital trainer. The seven outputs, "a out" to "g out" are connected to the corresponding inputs, "a" to "g", on the seven segment display.
0 Volt [pin 8] on the 16 pin driver circuits connector must be connected to 0 Volt on the Digital trainer. This links the 0 volt of all the seven driver circuits to the same 0 volt as the digital logic curcuits on the trainer.

Connecting a segment
[The connections for segment "a" are described here as an example.]
  • Segment "a" output from decoding cicuit on digital trainer
  • Input to "a" on the display driver circuit [pin 1]
  • Output from "a out" on display driver circuit [pin 13]
  • Input to "a" on seven segment display [pin 1]

NOTE: The connection marked "Common" on [pin 14] of seven segment display must be connected to the +V supply from the digital trainer.

It is called "Common" as it is connected to the anode of each of the LEDs in the seven segment display.

MONITOR OUTPUTS

This connection strip provides access to "a" to "g" segment signals and 0 Volts coming into the driver circuit.
NOTE: + V [pin 16] of the driver circuit connector needs a connection to +V on the digital trainer to make it available on the MONITOR OUTPUT strip.

The MONITOR OUTPUT strip will be needed for the final part of this trial using the 4511 CMOS BCD-to-7-Segment Latch Decoder Driver chip.


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4. The use of a CMOS 4511 BCD to 7 Segment Latch Decoder Driver as part of Practical Task.

This final section of Trial1 uses a CMOS 4511 BCD to 7 segment decoder chip to do what we have been building during this trial. The internal circuit diagram of the chip in the data sheet shows the decoding circuits for the 7 segments for the digits "0" to "9". Four bits are needed to encode these digits as binary values 0000 to 1001. This use of 4 bit binary to encode each decimal number is called BINARY CODED DECIMAL, abreviated to BCD.

The inputs on the 4511 chip marked "A" to "D" are the four bits of the BCD with "A" being the least significant bit. The outputs "a" to "g" are the seven segment drive signals.

FOR THE REST OF TRIAL1 THE VALUES OF THE FOUR INPUTS SHOULD BE "A" = SWITCH A on the trainer, "B" = SWITCH B on the trainer, "C" = 0V from the trainer and "D" = 0V from the trainer. THE POWER SUPPLY TO THE CHIP IS CONNECTED "Vdd", pin 16, = +V from the trainer and "Vss", pin 8, = 0V from the trainer.



There are two different types of 7 segment display, one has all the Anodes of the 7 leds connected together called COMMON ANODE, or CA. The other type has all the cathodes of the 7 leds connected together called COMMON CATHODE, or CC.

The display we have been working with is a CA type where the display is connected to +V and the segments are lit by connecting each individual led to 0 V via a resistor. This task in our system was carried out by the PCB with the seven transistors stages. We will still need to use this PCB between the outputs "a" to "g" on the 4511 chip and the 7 segment display. This is because the chip is designed for CC type displays.

Fortunately, we have the inputs to PCB on the terminal strip, so "a" out from the CMOC 4511 chip goes to "a" on the PCB terminal strip, "b" on the chip to "b" on the strip ending with "g" on the chip connecting to "g" on the terminal strip and the PCB connects to our 7 segment as before. The connection diagram in trial1_building has the connections on a prototype board as extra help.



4511 CMOS BCD-to-7-Segment Latch Decoder Drivers


The NOT LT is a LAMP TEST and will put all the segment outputs HIGH to test the led display when connected to 0V, and work normally when it is connected to +V. NOT BL is BLANKING and will force all segment ouputs LOW to the led display when connected to 0V, and work normally when it is connected to +V. The LE / NOT STROBE is LATCH ENABLE when connected to 0V and STROBE when connected to +V. In this trial we will connect it to 0V. This "enables" segment outputs to react instantly to changes in the inputs A, B, C and D. The LATCH will be the first circuit to be examined in trial2 and details of how it works will be covered then.